Complete analysis of your IC Package and its test board.  We will tell you the I/O s-parameters, eye diagram and jitter performance. If your s-parameters are not satisfactory we will tell you where in the interconnect path is causing return loss degradation and suggest design changes to improve performance. Typical Test & Model Objectives TDR (S11) measured to IC input Transceivers Partition TDR into exact component models (e.g. via) Optimize Hspice simulation to match S11 measurement Simulate TDT/S21 for 1ns eye diagram Differentiate IC performance by Eye & S-parameters Differentiate IC performance by S11/S21 crossover Use IConnect Analysis to convert Time Domain Simulations to Impedance, S parameters and Eyes Use Analysis to define network S11 Pass/Fail test USB Package and DUT Board Setup In this test example, a USB device test board and package was failing functional test. The customer wanted to know what the s-parameters were on the I/O and the input C of the package as they needed to know if their device was failing functional test or if it was the IC package or its DUT test board.   We used IConnect and advanced Spice techniques to analyze each interconnect component and report where the board and package could be improved to pass specified S- parameters and eye diagram tests.  Above is the diagram of the test setup and below, the related measurements.  Click HERE to get the full report. We can perform this kind of analysis on your IC package and DUT test board.  Click HERE to email your questions. TDR Analysis of IC Package and DUT Test Board